Video signal processor

ABSTRACT

A phase control circuit sets the phase of a sampling clock signal for A/D conversion of a video signal in order. A binarizing circuit binarizes an analog video signal. A first counter circuit counts the changes of the output signal of the binarizing circuit. An A/D converting circuit digitizes the input signal. A second counter circuit counts the changes of the most significant bit of the A/D converting circuit. A subtracting circuit subtracts one from the other of the output signals of the two counter circuits. By changing the phase of the sampling clock signal of the A/D conversion in order within one period, the subtraction results are found, and this process is repeated for one or more periods. Thus the phase of the optimum sampling clock is set according to the subtraction results.

TECHNICAL FIELD

The present invention relates to a video signal processing apparatuswhich converts an analog video signal to a digital signal.

BACKGROUND ART

Recently, a liquid crystal display device is mainly developed as a videoapparatus to replace a cathode ray tube (CRT) display therewith. Videosignals received from a personal computer by a display device such as aliquid crystal display (LCD) device are analog signals, and the signallevel thereof changes in the unit of dot period. Therefore, a samplingclock signal matching to the dot period is needed for signal processingwhen the signal is written to a memory, when the signal is displayed ona matrix display device, and the like. However, most personal computersdo not have an output terminal of such a sampling clock signal.Therefore, it is necessary to reproduce the sampling clock signal basedon horizontal synchronization signal or the like received from acomputer or the like. Further, the analog video signal cannot beobtained correctly if it is not sampled at a timing in a dot period whena stable signal is outputted. Therefore, the sampling timing has to beappropriate. Then, an appropriate timing of the sampling clock signal isset manually.

In a video apparatus, the sampling clock signal can be reproduced with aphase-locked loop (PLL) circuit by multiplying the input horizontalsynchronization signal and by making both frequency and phase match tothose of the input signal. However, the output signal of the PLL circuithas a phase delay because the timing signal required for display controlis generated in a logic circuit at a later stage. Because this phasedelay depends on the frequency of the input signal, it can notdetermined uniquely in a video apparatus which can receive various inputsignals. Therefore, scattering of the timing signal due to phase delayis a problem, especially on sampling.

In order to optimize the sampling point, a video information apparatusdisclosed in Japanese Patent laid open Publication 9-149291 (1997) usesauto-correlation of video signals between frames. That is, a delay timeof sampling clock signal is changed successively, and theauto-correlation between frames of video signals after analog-to-digitalconversion is determined for each delay time. Then, a point having lowcorrelation is adopted as a point at which the signal is changed. Then,by changing the sampling clock delay, an optimum sampling point isdetermined at a midpoint or thereabout of the signal-changing point.However, this conventional optimizing circuit needs a frame memory inorder to determine the correlation value. Therefore, a complicatedmemory control circuit and high-speed clock signal are needed. A methodusing multiple A/D converter circuits is known as a method not using amemory. However, this method has a problem that a plurality of delaycircuits for sampling clock are necessary.

An object of the invention is to provide a video signal processingapparatus which optimizes the sampling point when an analog video signalis converted to a digital signal.

DISCLOSURE OF THE INVENTION

A first video signal processing apparatus according to the presentinvention comprises:

a clock generator which generates a sampling clock signal for digitizinga video signal based on an input synchronization signal;

a phase controller which controls phase of the sampling clock signal atone of a plurality of phases in one period of the sampling clock signal;

a first signal generator which generates a first signal when the inputvideo signal is larger than a threshold level;

a first counter which counts the first signal received from the firstsignal generator in a predetermined time;

a second signal generator which generates a second signal when the inputvideo signal is larger than another threshold level, at a timingaccording to the sampling clock signal controlled by the phasecontroller;

a second counter which counts the second signal received from the secondsignal generator in the predetermined time; and

a controller which makes the phase controller sequentially change thephase of the sampling clock signal in a period of the sampling clocksignal, repeats the phase change over one or more periods of thesampling clock signal and sets the phase of the optimum sampling clocksignal based on a difference between the output signals of the first andsecond counters obtained for each of the changed phases.

For example, the controller set the optimum phase of the sampling clocksignal according to a plurality of the subtraction results obtained bythe subtractor which performs subtraction between the output signals ofthe first and second counters. Thus, the phase of the sampling clocksignal can be controlled by using a simple structure that the times ofthe cases when the video signal exceeds the threshold level is countedby the two counters. Further, timing control of the output signal of thebinarizer circuit and that of an analog-to-digital converter are notneeded. Further, high speed sampling clock signal is not needed tocontrol the phase of the sampling clock signal, so that consumptionpower can be decreased. Further, because the sampling clock signal isnot needed after the output of the binarizer circuit and theanalog-to-digital converter, the counters can process a high speedsignal. Therefore, this decreases consumption power and is advantageousfor fabricating a large scale integrated circuit thereof.

In the video signal processing circuit, the optimum sampling clocktiming can be set in various ways. For example, the controller sets aphase of the sampling clock signal, at which an absolute value of thecount values of the first and second signals is equal to or smaller thana predetermined value, to the phase of optimum sampling clock signal.Alternatively, the controller sets a phase of the sampling clock signal,at which an absolute value of the count values of the first and secondsignals is equal to or smaller than a predetermined value and theabsolute value is smallest, to phase of optimum sampling clock signal.Alternatively, the controller makes the phase controller changesequentially the phase of sampling clock signal in a period of thesampling clock signal, and when the controller continuously detects aphase of the sampling clock signal, at which an absolute value of countvalues of the first and second signals is equal to or smaller than apredetermined value, the controller sets a center value of thecontinuously detected phases of the sampling clock signal to the phaseof optimum sampling clock signal. Alternatively, the controller makesthe phase controller change sequentially the phase of sampling clocksignal in a period of the sampling clock signal, and when the controllerdetects two or more phases of the sampling clock signal, at which anabsolute value of count values of the first and second signals becomesmaximum, the controller sets a center value of the two or more phases ofthe sampling clock signal to the phase of optimum sampling clock signal.

Further, in the video signal processing circuit, the controllerpreferably stops to control the phase controller when the output valueof the first counter is equal to or smaller than a predetermined value.Thus, the phase control is stopped for video signal which does notchange much, so that malfunction is prevented when the optimum samplingpoint is detected.

Further, in the video signal processing circuit, the controllerpreferably further comprises a threshold level controller which controlsthe threshold level of the first signal generator, and a comparatorwhich compares the output signal of the second signal generator with adifferent threshold level. The controller decides whether the outputvalue of the first counter is equal to or smaller than the predeterminedlevel. Then, it decreases the threshold levels of the first signalgenerator and of the comparator when the output value of the firstcounter is equal to or smaller than the predetermined value. The outputof the first counter is equal to or smaller than the predetermined valuewhen the video signal has low level. Then, in such a case, the level forsignal detection is decreased, so that the optimum sampling point can bedetected even when the video signal has low level.

In a first video signal processing method according to the invention, asampling clock signal is generated for digitizing a video signal basedon an input synchronization signal, and phase of the sampling clocksignal at one of a plurality of phases is changed sequentially in oneperiod of the sampling clock signal. The phase setting is repeated overone or more periods of the sampling clock signal, and for each of thephase setting, a first signal is generated when the input video signalis larger than a threshold level and the first signal is counted in apredetermined time. Further, a second signal is generated when the inputvideo signal is larger than another threshold level at a timingaccording to the sampling clock signal, and the second signal is countedin a predetermined time. Then, a phase of optimum sampling clock signalis set based on differences between the count values obtained byrepeating the phase change.

In the video signal processing method, preferably, the phase control isstopped when the count value of the first signal is decided to be equalto or smaller than a predetermined value.

In the video signal processing method, preferably, when the count valueof the first signal is decided to be equal to or smaller than apredetermined value, threshold levels for the first and second signalsare decreased.

A second video signal processing apparatus according to the inventioncomprises:

a signal generator which binarizes an input video signal;

a clock generator which generates a sampling clock signal based on aninput synchronization signal;

a phase controller which controls phase of the sampling clock signal atone of a plurality of phases in one period of the sampling clock signal;

a delay circuit which delays an output signal of the signal generator byone sampling period;

a maximum detector which receives the output signal of the signalgenerator and that of the delay circuit and performs subtraction of thetwo output signals to provide a maximum value of the absolute value ofthe subtraction; and

a controller which makes the phase controller sequentially change thephase of sampling clock signal by the phase controller in a period ofthe sampling clock signal, repeats the phase setting over one or moreperiods of the sampling clock signal to decide the largest value indistribution of maximum values detected by the maximum detector and setsthe phase of the largest value to an optimum sampling point. Accordingto this invention, the sampling timing can be controlled by using asimple structure where subtraction results are obtained on video signalaround one sampling, and distribution of absolute value of maximum valueis detected. Further, by detecting the distribution of absolute value ofmaximum value, change in signal level can be detected, and correctsampling phase can be set.

In a second video signal processing method according to the invention, asampling clock signal which digitizes a video signal is generated basedon input synchronization signal, and phase of the sampling clock ischanged sequentially at one of a plurality of phases in one period ofthe sampling clock signal. For each of the phase change, the input videosignal is binarized, and the binarized signal is delayed by one samplingperiod, and the binarized signal. The delayed signal are received in apredetermined time and subtraction of the two output signals isperformed to detect a maximum value of the absolute value ofsubtraction. Then, the largest value is decided in distribution of thedetected maximum values, and the phase of the largest value is set to anoptimum sampling point.

A third video signal processing apparatus according to the inventioncomprises:

a clock generator which generates a sampling clock signal based on aninput synchronization signal;

a phase controller which controls phase of the sampling clock signalgenerated by the clock generator;

a signal generator which receives a video signal which changesalternately at a frequency of the sampling clock signal and binarizesthe video signal at a timing of the sampling clock signal;

a two-phase processor which subjects an output signal of the signalgenerator to two-phase processing;

a plurality of level change detectors which detect the existence oflevel change for a plurality of output signals of the two-phaseprocessor; and

a controller which makes the phase controller change phase of thesampling clock sequentially and sets a phase, at which any of the levelchange detectors does not detect level change, to an optimum samplingpoint. Therefore, the sampling clock can be optimized at low speedprocessing.

In a third video signal processing method according to the invention, asampling clock signal for digitizing a video signal is generated basedon an input synchronization signal, and phase of the sampling clocksignal is changed sequentially in a period of the sampling clock signal.The phase change is repeated over one or more periods of the samplingclock signal, wherein for each of phase change, a video signal whichchanges alternately at a frequency of the sampling clock signal isreceived, the video signal is binarized at a sampling timing of thesampling clock signal, the binarized signal is subjected to two-phaseprocessing, and the level change is detected for a plurality of theoutput signals obtained in the two-phase processing. Then, a phase, atwhich the level change is not detected for any of the output signals, isset to an optimum sampling point.

This summary of the invention does not necessarily describe allnecessary features so that the invention may also be a sub-combinationof these described features.

BRIEF EXPLANATION OF THE DRAWINGS

FIG. 1 is a block diagram of a video signal processing apparatusaccording to a first embodiment of the present invention;

FIG. 2 is a circuit diagram of a phase controller circuit;

FIG. 3 is a flowchart of control of a first decision circuit;

FIG. 4 is a waveform diagram of the video signal processing apparatusaccording to the first embodiment of the present invention;

FIG. 5 is a block diagram of a video signal processing apparatusaccording to a second embodiment of the present invention;

FIG. 6 is a block diagram of a video signal processing apparatusaccording to a third embodiment of the present invention;

FIG. 7 is a flowchart of control of a first decision circuit;

FIG. 8 is a block diagram of a video signal processing apparatusaccording to a fourth embodiment of the present invention;

FIG. 9 is a flowchart of control of a fourth decision circuit;

FIG. 10 is a block diagram of a video signal processing apparatusaccording to a fifth embodiment of the present invention;

FIG. 11 is a timing chart of two-phase processing; and

FIG. 12 is a flowchart of control of a fifth decision circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of a video signal processing apparatus according to thepresent invention are described in detail below with reference to theappended drawings, wherein like reference characters designate like orcorresponding parts throughout the several views.

FIG. 1 shows a video signal processing apparatus according to a firstembodiment of the present invention. The video signal processingapparatus is for example a liquid crystal display device. In the videosignal processing apparatus of the embodiment, an input analog videosignal is compared with a threshold level by a binarizing circuit 6 andan analog-to-digital (A/D) converter circuit 2, and two counters 7, 8count times when a video signal is changed over the threshold level, ina predetermined time. The A/D converter 2 performs the conversion at acontrolled phase of sampling clock signal. Thus, the binarizing circuit6 and the A/D converter 2 perform the comparison with the thresholdlevel at different timings. When the phase of sampling clock signal isappropriate, there is no difference between the two counts, but when thephase is not appropriate, the difference between the two counts becomeslarge. Then, as to the sampling clock signal, a plurality of phases (forexample, four phases) or sampling timing can be selected sequentially inone period of sampling clock signal. Then, a phase controller circuit 5selects the phase sequentially in one period, and the above-mentionedtwo counts are determined for each of the selectable phases (samplingtimings) in a predetermined time (equal to or longer than one period).Then, differences between the counts obtained for each of the selectablephases are compared, and the phase at which the difference becomessmaller than a predetermined value is set to an optimum phase forprocessing video signals.

This is further explained in detail with reference to FIG. 1. An inputvideo signal 1 is supplied to the A/D converter 2. On the other hand, asampling clock signal 70 is generated based on a synchronization signal(for example a horizontal synchronization signal) 3 by the phase-lockedlogic (PLL) circuit 4 and the phase controller 5. The PLL circuit 4generates a sampling clock signal based on the synchronization signal.As shown in FIG. 2, the phase controller 5 comprises three delayelements 51, 52 and 53 connected in series and a selector 54. Bycontrolling the selector 54 according to a phase control signal 90, foursignals of different phases can be outputted in one period of samplingclock signal. That is, the phase controller 5 outputs a clock signal ofa phase in correspondence to the phase control signal 90 to the A/Dconverter 2. The A/D converter 2 samples the input video signal 1 at thesampling clock timing due to the clock signal, and outputs an 8-bitdigital signal to an image processing circuit 11. The video processingcircuit 11 performs enlargement, reduction or the like and displays theobtained video data on a liquid crystal display panel 12.

Further, the input image signal 1 is also supplied to the binarizingcircuit 6 comprising a comparator. The binarizing circuit 6 compares itwith a predetermined level to binarize the input image signal 1, and abi-level output signal 60 is supplied to the first counter 7. (Forexample as shown in FIG. 4, the predetermined level is set to 0.5 V forvideo signal of 1 V.) Further, the topmost bit signal 80 from the A/Dconverter 2 is supplied to the second counter 8. The first and secondcounters 7, 8 count input signals in a predetermined time (for example,one vertical period or a plurality of horizontal periods) and supply theresults to a subtractor circuit 9. The topmost bit from the A/Dconverter 2 is binarized with the same level of threshold level as thebinarizing circuit 6. Therefore, the first and second counters 7, 8perform binarization with the same threshold level eventually to countthe change in video signal. (However, the threshold level is notnecessarily the same.) The subtractor 9 performs subtraction of thecount values from the first and second counters 7, 8 and supplies theabsolute value of the difference of the two count values to a firstdecider circuit 10. The first decider circuit 10 sequentially changesthe phase to be set by the phase controller 5 in a period and determinesat each different phase whether the absolute value supplied from thesubtractor 9 is within a predetermined range. The phase at which theabsolute value is within this range is set to the optimum samplingphase.

The first decider circuit has a central processing unit (CPU). Asexplained above, it sends a phase control signal 90 to the phasecontroller 5 to control the phase of sampling clock and to set theoptimum sampling clock for the second counter 8. FIG. 3 shows a flow ofsampling optimization by the CPU. First, the phase control signal 90 issent to the phase controller 5 to advance the selector 54 by one (stepS10), to set a sampling phase in a period of sampling clock signal.Next, the count values in the first and second counters 7, 8 are reset(step S12). Then, the two counters 7, 8 continue counting (step S14).The counting at step S14 is repeated until a predetermined time elapses(step S16). When the predetermined time elapses, it is decided whetherthe absolute values of the difference of the counts from the subtractor9 is smaller than a predetermined value or not (step S18). If theabsolute value of the difference of the counts from the subtractor 9 isequal to or larger than the predetermined value, the sampling phase isan anomalous one. Then, the flow returns to step S10, and the phase isreset to a next one to repeat the above processing. If the absolutevalue of the difference of the counts from the subtractor 9 is smallerthan the predetermined value, the sampling phase is decided to be anoptimum one (step S20). Thus, the optimum phase of the sampling clocksignal is set.

FIG. 4 shows waveforms of signals in the video signal processingapparatus. With reference to the waveforms, operation is explained whenthe sampling phase is appropriate and when it is inappropriate. In thevideo signals shown in FIG. 4, vertical solid line represents basicphase, while dashed lines represent three phases obtained by delay. Thesampling phase is controlled at four values in one period of samplingclock by the phase controller 5. The phase of the phase controller 5 ischanged sequentially in one period of the sampling clock, and this isrepeated over one or more periods of sampling clock. In correspondenceto the four phases, the topmost bit outputted by the A/D converter 2which digitized the video signal is changed, as shown in FIG. 4 as A, B,C and D. In case of A, sampling is performed at sampling points 51, 55and the like. Similarly, in case of B, sampling is performed at samplingpoints 52, 56 and the like, in case of C, sampling is performed atsampling points 53, 57 and the like, and in case of D, sampling isperformed at sampling points 54, 58 and the like. In the case of C, theoutput signal 80 of the A/D converter 2 becomes most unstable becausesampling is performed at a changing portion in the input signal.Therefore, as will be understood by comparing the bi-level signal 60with the topmost bit 80, the output data of the first counter 7 isdifferent largely from that of the second counter 8, and the subtractionresult or difference of a large value is supplied to the first decider10. The first decider 10 decides that a sampling point at which theabsolute value of the output value of the subtractor 9 is equal to orlarger than the predetermined value is a bad sampling point. In the caseof C, the sampling phase is inappropriate. The phase controller 5controls the phase at a plurality of sampling points, and the optimumsampling point is decided by the first decider 10 based on the pluralityof subtraction results. In the example shown in FIG. 4, the value ofsubtraction result is large for C and small for A, B and D. By settingan appropriate value, a phase at least satisfying that the absolutevalue of the subtraction result is smaller than the predetermined valueis selected as the optimum sampling phase.

The optimum sampling phase can be selected in various ways. For example,when there are a plurality of cases where the absolute values of thesubtraction result is equal to or smaller than the predetermined value,a phase in correspondence to the smallest value among them may beadopted.

Alternatively, when there are a plurality of cases where the absolutevalue of the subtraction result is equal to or smaller than thepredetermined value, a center thereof may be set to the optimum samplingphase. Thus, the sampling point can be set more stably.

As mentioned above, the phase of the phase controller 5 is changedsequentially in one period of sampling clock, and this is repeated overone or more periods. When two or more phases are found to have themaximum subtraction result (for example, phase 53 in FIG. 4), the centerthereof may be set to the optimum phase.

By controlling the phase of sampling clock signal sequentially to detectthe largest and the smallest in one period of sampling clock signal, theset value for the first decider 10 may be determined as the differencebetween the largest and smallest values multiplied with a predeterminedfactor.

Further, the difference between the two count values may be detectedgenerally with a different calculation technique, without using thesubtractor.

In the above-mentioned video signal processing apparatus, the optimumphase can be set with a low-cost circuit structure because the binarizedsignals are used. Further, it is not necessary to adjust the outputsignal of the binarizing circuit with a digital circuit following theA/D converter. Further, because the number of level change is detected,a PLL circuit does not need to output a high-speed sampling clock, andlow power consumption can be achieved. The adjustment of the samplingtiming becomes important as the frequency of video signal is increased,while the video signal processing apparatus can optimize the samplingpoint even when the frequency becomes higher.

FIG. 5 shows a structure of a video signal processing apparatusaccording to a second embodiment of the present invention. In the videosignal processing apparatus according to the first embodiment shown inFIG. 1, the detection of the optimum sampling point may be operatederroneously for video information which does not change much. Then, inthe video signal processing apparatus according to this embodiment, theabove-mentioned optimum phase setting of sampling clock is not performedfor video information which does not change much.

As shown in FIG. 5, a second decider 13 and a phase control stoppercircuit 14 are provided further. The second decider 13 has a comparator,which compares the count value outputted by the first counter 8 with apredetermined value. When the count value is equal to or smaller thanthe predetermined value, a phase control stop signal 100 is sent to thephase control stopper circuit-14 in order to stop to output the phasecontrol signal 90. The phase control stopper circuit 14 has a switchwhich passes the phase control signal 90, and the switch is controlledby the phase control stop signal 100.

The operation is explained further. For ordinary video signals, thephase control stopper circuit 14 does not receive the phase control stopsignal 100 because the count value outputted by the first counter 8 isequal to or larger than the predetermined value. In this case, the phasecontrol stopper circuit 14 sends the phase control signal 90 as receivedfrom the first decider 10 to the phase controller 5. Then, the phasecontroller 5 controls the phase sequentially according to the phasecontrol signal 90 and sets the optimum sampling phase.

On the contrary, when the count value outputted by the first counter 8is found to be smaller than the predetermined value, the phase controlstopper circuit 14 receives the phase control stop signal 100 from thesecond decider 13. Then, the phase control stopper circuit 14 stops tooutput the phase control signal 90 received from the first decider 10.When the count value outputted by the first counter 8 is equal to orsmaller than the predetermined value, this means that the video signaldoes not change much. In such a case, in order to avoid malfunction inthe detection of optimum sampling point, the optimization of samplingtiming is not performed. Thus, the phase control is stopped by the phasecontrol stopper circuit 14 when the output signal of the first counter 8is equal to or smaller than the predetermined value. Then, malfunctionof the detection of optimum sampling point is prevented for video signalwhich does not change much.

FIG. 6 is a block diagram of a video signal processing apparatusaccording to a third embodiment of the present invention. In the videosignal processing apparatus, the optimum sampling point is detected evenwhen the video signal has a small level. A third decider circuit 17 isprovided to decrease the threshold level of the binarizing circuit andthat for the digital value outputted by the A/D converter to detect theoptimum sampling point.

The video signal processing apparatus has a binarization levelcontroller circuit 15, a comparator 16 and a third decider circuit 17.The binarization level controller circuit 15 converts the thresholdlevel from the third decider circuit 17 to an analog level and outputsit to a threshold level of the binarization circuit 6. Further, thecomparator 16 compares the output signal of the A/D converter 2 with thethreshold level from the third decider 17. The third decider 17 has aCPU and detects the optimum sampling point even when the video signalhas a small level, by setting a small threshold level for binarizationin the binarization circuit 6 and the comparator 16. Further, when thevideo information has a small level (or when video information equal toor larger than a predetermined value is not detected), the third decider17 outputs a phase control stop signal 110 to the phase control stoppercircuit 14 to stop the adjustment of the optimum sampling point. In thiscase, it is informed to an operator with a video image, an audio signal,a light-emitting diode or the like. The phase control stopper circuit 14has a switch to pass the phase control signal 90, and the switch iscontrolled with the phase control stop signal 110. Thus, an optimumsampling point can be set, similarly to the video signal processingapparatus of the first embodiment.

FIG. 7 shows a flow of control by the CPU of the third decider 17.First, a count value output from the first counter 8 is compared with apredetermined value (step S20). If the value outputted by the firstcounter 8 is equal to or larger than the predetermined value, the phasecontrol stop signal 110 is not outputted (step S30). Then, the phasecontrol stopper circuit 14 sends the as-received phase control signal 90from the first decider 10 to the phase controller 5, and the phasecontroller 5 controls the phase sequentially with the phase controlsignal 90 and sets the optimum sampling phase. This is the control forordinary video signal.

On the contrary, if the value outputted by the first counter 8 issmaller than the predetermined value, the phase control stop signal 110is sent to the phase control stopper circuit 14 (step S22). Then, thephase control stopper circuit 14 stops to output the phase controlsignal 90 received from the first decider 10 to the phase controller 5.Further, the third decider 17 decreases the threshold level (analogvalue) for binarization in the binarization level controller 15 (stepS24), and it is decided again whether the output value from the firstcounter 8 is equal to or larger than the threshold value or not (stepS26). If it is decided that the output value from the first counter 8 issmaller than the threshold value even after the threshold value is setlower, the flow returns to step S24 to change the threshold value again.If the value outputted by the first counter 8 is decided equal to orlarger than the predetermined value, the threshold level is supplied tothe comparator 16 (step S28). Then, the digital output signal from theA/D converter 2 is compared with the same threshold level as thebinarization circuit 6, to give a bi-level value. Next, A the phasecontrol stop signal 110 is stopped to be supplied to the phase controlstopper circuit 14 (step S30), and the control of the optimum samplingpoint is performed. That is, the phase control stopper 14 sends thephase control signal 90 to the phase control circuit 5 to adjust theoptimum sampling point. Thus, when the count value of the first counter8 is equal to or smaller than the predetermined value, the third decider17 changes the threshold level of the binarization in the binarizationcircuit 6 and that in the comparator 16, so that the optimum samplingpoint can be detected even when the video information is small.

Next, a video signal processing apparatus according to a fourthembodiment of the present invention is explained. In the video signalprocessing apparatus, the subtraction result of video signals around asampling timing is determined by changing the phase. The largest in theabsolute values of the subtraction results corresponds to a phase atwhich the change in signal level is largest. Then, the phase incorrespondence to the largest value in the distribution of the absolutevalues of the maximum values is set to the optimum sampling point.

FIG. 8 is a block diagram of the video signal processing apparatus ofthe fourth embodiment. The phase controller 5 controls the phase of thesampling clock signal from the PLL circuit 4 and supplies it to the A/Dconverter 2 and to a delay circuit 20. The A/D converter 2 digitizes theinput video signal 1. The delay circuit 20 has a delay flip-flop (D-FF)operated with the sampling clock signal, and it delays the topmost bitof the output signal of the A/D converter 2 by one sampling clockperiod. A subtractor 21 receives output signals from the A/D converter 2and from the delay circuit 20 and performs subtraction between them tosend the result to a maximum detector circuit 22. The maximum detector22 detects a maximum in the absolute values of the subtraction valuearound one sampling and sends it to a fourth decider 23. The fourthdecider 23 sends a phase control signal to the phase controller 5 tocontrol the phase of the sampling clock signal sequentially and todecide a phase at the largest among the maximum values detected by themaximum detector 22. Then the largest value is set to the optimumsampling point for the phase controller 15. Thus, by using a simplecircuit structure where the maximum value of the subtraction value ofvideo signal around one sampling is detected, the optimum sampling pointcan be detected. By detecting distribution of the maximum values, changein signal level can be detected, and a correct sampling phase is set. Itcan also be detected simultaneously that the video signal is made ofconstant level such as all white, and malfunction can be prevented.

FIG. 9 shows a flow of control of a CPU in the fourth decider 22. First,the phase control signal 90 is sent to the phase controller 5 to set afirst sampling phase in one period of sampling clock signal (step S50).Next, a maximum of the absolute value of the difference of video signalsaround one sampling is determined (step S52). Next, it is checkedwhether the measurement is completed on all the sampling phases whichcan be set in one period (step S54). If it is checked that themeasurement is not completed, the flow returns to step S50, to set thephase control signal for a next sampling phase and the absolute value ofthe difference is received. If it is checked that the measurement iscompleted on all the sampling phases, the phase control signal isdetermined for the phase to result in the largest in the maximum valuesof the absolute value of the difference is determined in the phases inone period (step S56).

Next, a video signal processing apparatus in a fifth embodiment of theinvention is explained. As shown in FIG. 10, in the video signalprocessing apparatus, the optimum sampling timing is adjusted by using aparticular video signal 30 which changes alternately at the period ofsampling frequency. The phase controller 5 adjusts the phase of samplingclock signal generated by the PLL circuit 4. The A/D converter 2digitizes the particular video signal 30. Next, one or a plurality ofbits in the output signal of the A/D converter 2 is processed in twolines by a two-phase processor circuit. In the two-phase processorcircuit, the signal from the A/D converter 2 is sent to delay flip-flops(D-FF) 34, 35 in the two lines. Further, inverters 31, 33 and a ½frequency demultiplier 32 generates a clock signal of a frequency halvedon the sampling clock signal and an inverted clock signal, which aresupplied to the delay flip-flops (D-FF) 34 and 35, respectively, asclock signals. A timing chart shown in FIG. 11 shows output signals ofeach circuit. For example, if the input signal (an output signal of A/Dconverter) is changed at the sampling period alternately between whiteand black, output signals of the two lines subjected to the two-phaseprocessing (outputs of the delayed flip-flops 35, 34) are necessarily atconstant levels (white, white, white, . . . , or black, black, . . . )as far as the sampling timing is appropriate, or the level change isobserved. Level change detectors 36 and 37 detect change in outputsignal of the delay flip flop 34, 35, and the detection result of levelchange is supplied to a fifth decider circuit 38. For example, whenlevel change occurs, status signal of “1” is sent to the fifth decider38. In this case, the fifth decider 38 decides that the sampling pointis bad and sets the phase control for the phase controller 5. On thecontrary, when no level change occurs, the optimum sampling point isdecided to be set, and the phase where no level change occurs is set tothe optimum sampling point. Thus, the optimum sampling point can bedetected with a simple two-phase processing by receiving the particularvideo signal. Further, the level change can be detected with a low speedprocessing, and this is advantageous for fabricating the processingcircuit in an integrated circuit. The two-phase processing circuit mayberealized in various circuit structures besides the example shown in FIG.10.

FIG. 12 shows a flow of the control of a CPU in the fifth decider 38.First, the particular video signal 30 which changes between black andwhite at the period of sampling frequency is started to be received(step S70) Next, the phase control signal 90 on the phase of samplingclock signal is changed to be sent to the phase controller 5 (step S72). Next, level change is monitored on the signal subjected to thetwo-phase processing by the level change detectors 36, 37 (step S74),and it is decided whether level change occurs or not (step S76). Whenlevel change is detected, because the sampling point is bad, the flowreturns to step S72 to set a next sampling phase to continue themonitoring. When no level change is detected, it is decided next whethera predetermined time is completed or not (step S78). If it is decidedthat the predetermined time is not completed, the flow returns to stepS74 to continue the monitoring. If it is decided that the predeterminedtime is completed, it is decided to be an optimum sampling point, andthe phase is set to the optimum sampling phase (step S80).

Although the present invention has been described in connection with thepreferred embodiments thereof, it is to be noted that the scope of theinvention is described in the appended claims and that various changesand modifications included therein are included in the presentinvention.

What is claimed is:
 1. A video signal processing apparatus comprising: aclock generator which generates a sampling clock signal for digitizing avideo signal based on an input synchronization signal; a phasecontroller which controls phase of the sampling clock signal at one of aplurality of phases in one period of the sampling clock signal; a firstsignal generator which generates a first signal when the input videosignal is larger than a threshold level; a first counter which countsthe first signal received from the first signal generator in apredetermined time; a second signal generator which generates a secondsignal when the input video signal is larger than another thresholdlevel, at a timing according to the sampling clock signal controlled bysaid phase controller; a second counter which counts the second signalreceived from the second signal generator in the predetermined time; anda controller which makes said phase controller sequentially change thephase of the sampling clock signal in a period of the sampling clocksignal, repeats the phase change over one or more periods of thesampling clock signal and sets the phase of the optimum sampling clocksignal based on a difference between the output signals of said firstand second counters obtained for each of the changed phases.
 2. Thevideo signal processing apparatus according to claim 1, wherein saidfirst signal generator comprises a binarizing circuit which converts theinput video signal to a bi-level signal, and said second signalgenerator comprises an analog-to-digital converter which digitizes theinput video signal.
 3. The video signal processing apparatus accordingto claim 1, wherein said controller sets a phase of the sampling clocksignal, at which an absolute value of the count values of the first andsecond signals is equal to or smaller than a predetermined value, to thephase of optimum sampling clock signal.
 4. The video signal processingapparatus according to claim 1, wherein said controller sets a phase ofthe sampling clock signal, at which an absolute value of the countvalues of the first and second signals is equal to or smaller than apredetermined value and the absolute value is smallest, to phase ofoptimum sampling clock signal.
 5. The video signal processing apparatusaccording to claim 1, wherein said controller makes said phasecontroller change sequentially the phase of sampling clock signal in aperiod of the sampling clock signal, and when said controllercontinuously detects a phase of the sampling clock signal, at which anabsolute value of count values of the first and second signals is equalto or smaller than a predetermined value, said controller sets a centervalue of the continuously detected phases of the sampling clock signalto the phase of optimum sampling clock signal.
 6. The video signalprocessing apparatus according to claim 1, wherein said controller makessaid phase controller change sequentially the phase of sampling clocksignal in a period of the sampling clock signal, and when saidcontroller detects two or more phases of the sampling clock signal, atwhich an absolute value of count values of the first and second signalsbecomes maximum, said controller sets a center value of the two or morephases of the sampling clock signal to the phase of optimum samplingclock signal.
 7. The video signal processing apparatus according toclaim 1, wherein said controller stops to control said phase controllerwhen the output value of said first counter is equal to or smaller thana predetermined value.
 8. The video signal processing apparatusaccording to claim 1, further comprising: a threshold level controllerwhich controls the threshold level of said first signal generator; and acomparator which compares the output signal of said second signalgenerator with a different threshold level; wherein said controllerdecides whether the output value of said first counter is equal to orsmaller than the predetermined level and decreases the threshold levelsof said first signal generator and of said comparator when the outputvalue of said first counter is equal to or smaller than thepredetermined value.
 9. A video signal processing method comprising thesteps of: generating a sampling clock signal for digitizing a videosignal based on an input synchronization signal; sequentially changingphase of the sampling clock signal at one of a plurality of phases inone period of the sampling clock signal, and repeating the phase settingover one or more periods of the sampling clock signal, wherein for eachof the phase setting, the method comprising further the steps of:generating a first signal when the input video signal is larger than athreshold level and counting the first signal in a predetermined time;and generating a second signal when the input video signal is largerthan another threshold level at a timing according to the sampling clocksignal and counting the second signal in a predetermined time; andsetting a phase of optimum sampling clock signal based on differencesbetween the count values obtained by repeating the phase change.
 10. Thevideo signal processing method according to claim 9, wherein the phasecontrol is stopped when the count value of the first signal is decidedto be equal to or smaller than a predetermined value.
 11. The videosignal processing method according to claim 9, wherein threshold levelsfor the first and second signals are decreased when the count value ofthe first signal is decided to be equal to or smaller than apredetermined value.
 12. A video signal processing apparatus comprising:a signal generator which binarizes an input video signal; a clockgenerator which generates a sampling clock signal based on an inputsynchronization signal; a phase controller which controls phase of thesampling clock signal at one of a plurality of phases in one period ofthe sampling clock signal; a delay circuit which delays an output signalof said signal generator by on e sampling period; a maximum detectorwhich receives the output signal of said signal generator and that ofsaid delay circuit and performs subtraction of the two output signals toprovide a maximum value of the absolute value of the subtraction; and acontroller which makes said phase controller sequentially change thephase of sampling clock signal by said phase controller in a period ofthe sampling clock signal, repeats the phase setting over one or moreperiods of the sampling clock signal to decide the largest value indistribution of maximum values detected by said maximum detector andsets the phase of the largest value to an optimum sampling point.
 13. Avideo signal processing method comprising the steps: generating asampling clock signal which digitizes a video signal based on inputsynchronization signal; sequentially changing phase of the samplingclock at one of a plurality of phases in one period of the samplingclock signal; binarizing the input video signal; delaying the binarizedsignal by one sampling period; receiving the binarized signal and thedelayed signal in a predetermined time and performs subtraction of thetwo output signals to detect a maximum value of the absolute value ofsubtraction; and deciding the largest value in distribution of thedetected maximum values and setting the phase of the largest value to anoptimum sampling point.
 14. A video signal processing apparatuscomprising: a clock generator which generates a sampling clock signalbased on an input synchronization signal; a phase controller whichcontrols phase of the sampling clock signal generated by said clockgenerator; a signal generator which receives a video signal whichchanges alternately at a frequency of the sampling clock signal andbinarizes the video signal at a timing of the sampling clock signal; atwo-phase processor which subjects an output signal of said signalgenerator to two-phase processing; a plurality of level change detectorswhich detect the existence of level change for a plurality of outputsignals of said two-phase processor; and a controller which makes saidphase controller change phase of the sampling clock sequentially andsets a phase, at which all of said level change detectors do not detectlevel change, to an optimum sampling point.
 15. A video signalprocessing method comprising the steps: generating a sampling clocksignal for digitizing a video signal, based on an input synchronizationsignal; changing phase of the sampling clock signal sequentially in aperiod of the sampling clock signal, and repeating the phase change overone or more periods of the sampling clock signal, wherein for each ofphase change, a video signal which changes alternately at a frequency ofthe sampling clock signal is received, the video signal is binarized ata sampling timing of the sampling clock signal, the binarized signal issubjected to two-phase processing, and the level change is detected fora plurality of the output signals obtained in the two-phase processing;and setting a phase, at which the level change is not detected within apredetermined time among the plurality of the output signals obtained byrepeating the phase change, to an optimum sampling point.